1. Field of the Invention
The present invention relates to a memory device and a fabrication method thereof.
2. Description of Related Art
A memory device, such as a non-volatile memory device with a SONOS gate structure, for example, includes a charge trapping layer which stores charges in an isolated trap within the charge trapping layer. The non-volatile memory device may operate at a low operation voltage of 5-10V, and may have a simple device structure. Thus, the non-volatile memory device with a SONOS gate structure may be more easily fabricated in an effort to improve or achieve higher integration within a circuit.
FIG. 1 is a cross-sectional view illustrating a portion of a cell array area of a conventional NAND-type non-volatile memory device.
Referring to FIG. 1, a ground selection line 11G and string selection line 11S are disposed in parallel on a semiconductor substrate 1. A plurality of parallel word lines 11W are disposed between the ground selection line 11G and the string selection line 44S. A ground selection gate insulator 8G is interposed between the ground selection line 11G and the semiconductor substrate 1, and a string selection gate insulator 8S is interposed between the string selection line 11S and the semiconductor substrate 1. Similarly, a cell gate insulator 8C is interposed between each of the word lines 11W and the semiconductor substrate 1. The cell gate insulator 8C comprises a tunnel insulator 3, a charge trapping layer 5 and a blocking insulator 7 which are sequentially stacked. In addition, the string selection gate insulator 8S and ground selection gate insulator 8G have structure identical to cell gate insulator 8C.
Since the string selection gate insulator 8S, ground selection gate insulator 8G and cell gate insulator 8C of the conventional NAND-type non-volatile memory device have identical structure, threshold voltages of a string selection transistor and a ground selection transistor may be identical with an initial threshold voltage of a cell transistor. As a result, a voltage, higher than a threshold voltage of a MOS transistor used for a peripheral circuit area should be applied to a string selection line and a ground selection line in order to turn on the string selection transistor and ground selection transistor. However, the string selection transistor and ground selection transistor may be weakly programmed when a voltage exceeding threshold voltages of the string selection transistor and ground selection transistor is applied to the string selection line and/or the ground selection line. This in turn may cause threshold voltages of the string selection transistor and ground selection transistor to increase, leading to higher power consumption when driving the string selection transistor and the ground selection transistor.